1. Field of the Invention
This invention relates to a semiconductor device having a transistor of MOS structure and an opposite-polarity region under a channel region of the transistor, and a method of fabricating the same semiconductor device.
2. Description of the Related Art
As integration of semiconductor devices advances toward higher density, miniaturization of the devices continues. Although metal-oxide-semiconductor field effect transistors (MOS FET) are advantageous for integration, the power consumption of the semiconductor devices increases with the increasing degree of integration.
Accordingly, semiconductor devices having MOS structure are suitable when higher integration and low power consumption are both required. In addition, the demands of gate oxide reliability requires that the supply voltage be reduced for the semiconductor devices.
To implement the low supply voltage for semiconductor devices, it is necessary for a transistor to have a low threshold voltage V.sub.th to switch from on-state to off-state, or vice versa. In conventional semiconductor devices, however, there has arisen a problem in that some amount of leakage currents persist between the drain and source even at zero gate voltage.
In an attempt to obviate the above problem, there have been disclosed two transistor structures, in which, generally, a shallow well region is formed on a semiconductor substrate and just under a gate electrode, and by decreasing the depth of the shallow well region, a reverse bias capacitance between the semiconductor substrate and the well region is coupled with a depletion layer capacitance under the channel region, thereby achieving activation of the transistor at a substantially lower voltage.
These two structures will be described hereinbelow. One of the semiconductor structures has been disclosed in Japanese Laid-Open Patent Application No. 5-21730. According to the disclosure, as shown in FIG. 12 of the present application, a shallow well region 4A is formed on a surface region 5A of a semiconductor substrate and just under a gate electrode 1A, having a depth of 1.5 micron at most from the surface of the semiconductor substrate, and a MOS transistor is formed in a diffusion region 4A. By decreasing the depth of the region 4A, a reverse bias capacitance between a semiconductor substrate 5A and a well region 4A is coupled with a depletion layer capacitance under the channel region, which is controllable by a gate voltage applied to a gate electrode 1A. By this structure, a higher current between a source 3A and drain 2A has been obtained.
The other semiconductor structure has been disclosed in U.S. Pat. No. 5,489,795. According to the disclosure, as shown in FIG. 13 of the present application, a shallow well region 4B is formed on a surface region 5B of a semiconductor substrate and just under a gate electrode 1B, and a MOS transistor is formed in the diffusion region 4B, including a drain 2B, a source 3B, and the gate 1B.
In this structure, the depth of the shallow well from the surface of the substrate just under the gate electrode 1B is fabricated to be smaller than that under the drain 2B or source 3B, and a reverse bias capacitance between a semiconductor substrate 5B and a well region 4B is coupled with a depletion layer capacitance under the channel region. By this structure, activation of the transistor occurs at a substantially lower voltage, and thereby the drain current is more responsive to the applied gate bias voltage.
In the semiconductor devices with either one of the above-mentioned conventional structures, however, there has remained a problem that, because of a short distance between drain and substrate, some amount of leakage currents still persist between drain and substrate when a voltage is applied to the drain even at zero gate voltage, thereby resulting in the increase of standby currents of the devices.